Device for testing printed boards

ABSTRACT

The invention relates to a printed circuit board tester, more particularly for testing large-area non-componented circuit boards, comprising 
     a grid pattern provided with contact points arranged in a predetermined pattern, several contact points in each case being electrically connected to a straight-line scanning channel and an adapter and/or a translator being mounted of said grid pattern, 
     an electronic analyzer electrically connected to said contact points via said scanning channels, 
     a circuit board to be tested to which said adapter and/or said translator may be applied such that said adapter and/or translator produces an electrical contact of said circuit board test points on said circuit board to said contact points of said grid pattern, and 
     a means for electrically connecting at least two scanning channels.

The invention relates to a printed circuit board tester.

The invention is based on prior art according to EP 875 767 A2 which waspublished by the applicant of the present patent application, disclosinga test fixture comprising a plurality of test connections, in whichcircuit board test points of the board under test are in contact with atest connection via an electrical connection.

The electronic analyzer is electrically connected to a grid pattern onwhich an adapter and/or a translator is mounted on which a circuit boardto be tested may be placed. The adapter and/or translator produces anelectrical contact from the circuit board test points of the board undertest to contact points of the grid pattern.

This test fixture is characterized by at least two contact points beingelectrically connected to each other. More particularly, in this testerseveral contact points in each case are electrically connected to eachother along a straight-line scanning channel in each case. Theindividual scanning channels are electrically connected to an electronicanalyzer. Since each scanning channel is connected to several contactpoints the number of units of the electronic analyzer as compared to anelectronic analyzer of a comparable tester is considerably reduced andthe overall configuration of the test fixture becomes very simple.

Although in this test fixture several test points are electricallyconnected to a single scanning channel, it has been found outsurprisingly that in by far the majority of applications no doubleassignments of the scanning channels occur or that any such doubleassignments may be reliably obviated by dictating the assignment of thecircuit board test points to the contact points of the test fixture.This is achieved by the known tester creating a high contact pointdensity by relatively uncomplicated means, requiring for instance anaverage spacing of 800 μm or less between adjacent contact points. Thishigh circuit board test point density is of advantage since it permitscontacting a correspondingly high local circuit board test point densitywhilst, at the same time, making a sufficient redundancy available dueto the contact point density thus enabling a double assignment of ascapning channel to be reliably avoided.

The object of the present invention is to provide a simple and low-costtester for testing large-area circuit boards such as, for instance,backplanes sized e.g. 1000 mm×750 mm. Large-area circuit boards in thesense of the invention are circuit boards sized at least 500 mm×500 mm,i.e. having a surface area of at least 250,000 mm².

This object is achieved by a printed circuit board tester having thefeatures as they read from claim 1. Advantageous aspects read from thesub-claims.

The invention will now be detained by way of example embodiments withreference to the schematic drawings in which

FIG. 1 is a section through a portion or a grid base taken transverselyto the scanning channels,

FIG. 2 is a schematic illustration, greatly simplified, of the an arrayof scanning channels and of a bus board connecting several scanningchannels to each other, and

FIG. 3 is a front view of the arrangement as shown in FIG. 2 (i.e. asviewed in the direction of the arrow A therein).

The tester 1 in accordance with the invention comprises a grid base 2including a grid pattern 3 arranged on its upper side made up of aplurality of electrically conducting contact points 4 arranged in aregular pattern.

The grid base 2 is configured preferably as a laminated circuit board.The example embodiment as shown in FIG. 1 comprises a top and bottomdefining layer 5, 6 with thirteen intermediate layers 7 inbetween.

Extending from the contact points 4 vertically through the topmost layer5 and all intermediate layers 7 in each case is a verticalthrough-connection 8. The through-connections 8 are configured as a ruleas through-holes with a conductive metallized plating. Thethrough-connections 8 and thus the contact points 4 are arranged, forexample, in a regular square pattern, the grid pattern, having acenter-spacing of e.g. 1.27 mm, although, of course, other types of aregular pattern are possible.

The through-connections 8 and this the contact points 4 are accordinglyarranged in rows. Embedded in the grid base 2 between two rows ofthroughconnections connection 8 in each case are conductor paths 9,termed scanning channels in the following.

In the example embodiment as shown in FIG. 1 twelve such scanningchannels are provided in each case between two rows ofthrough-connections 8, each of the scanning channels 9 being arranged inpairs sandwiched between two intermediate layers 7. The scanningchannels 9 arranged in each case as twelve pairs adjacent to a row ofthrough-connections 8 are assigned to this row, i.e. eachthrough-connection 8 and thus each contact point 4 of any one row iselectrically connected to one of the scanning channels 9 assigned tothis row via a branch conductor 10. In the present example embodimenteach 24th contact point 4 in any one row is electrically connected ineach case to the same scanning channel 9.

FIG. 2 illustrates in a plan view the grid base 2 in accordance with theinvention, the grid pattern being illustrated greatly simplified by therun of the scanning channels 9 and without the contact points 4. To makefor an uncluttered illustration only a few of the scanning channels 9located parallel in a plane are shown.

The grid base 2 comprises a test zone 11 which is roughly square in theexample embodiment shown and a connection zone 12 extending beyond thetest zone 11. On the connection zone 12, the same as on the test zone11. contact points 4 as shown in FIG. 1 are provided on the top side aswell as contact points 13 on the bottom side, each of which iselectrically connected to the scanning channels 9 by means of thethrough-connections 8 and the branch conductors 10. Directly located onthe top side is a bus adapter 14 mounting in turn a bus board 15. Thebus board 15 comprises parallel bus conductors 16 oriented transverselyto the scanning channels 9. The bus conductors 16 are arranged eitherlocated open on the surface of the bus board 15 facing the bus adapter14 or electrically connected to the contact points arranged on thesurface of the bus board 15 on the center-spacing of the rows ofthrough-connections 8.

The bus adapter 14 comprises a plurality of contact pins 17, each ofwhich electrical connects a scanning channel 9 to a bus conductor 16.The intersection points of the scanning channels 9 electricallyconnected by a contact point 17 with the bus conductors 16 areidentified in each case in FIG. 2 by a circle 18. The contact pins 17are preferably configured as spring contact pins.

Providing the bus adapter 14 and the bus board 15 results in severalscanning channels 9 being electrically interconnected in each case viathe bus conductors 16.

Each array of electrically interconnected scanning channels 9 iselectrically connected to an electronics card 19 of the electronicanalyzer, i.e. only a single connection to the electronic analyzer isneeded for a plurality of scanning channels thus achieving a drasticreduction in the number of units of the electronic analyzer as comparedto conventional testers for the same number of contact points, sinceconventional testers require a separate connection for each contactpoint and thus a corresponding electronic analyzer processing capacityassigned to the connection.

The electronics cards are connected to the grid base electrically andmechanically e.g. by means of a flex conductor and spring pins as knownfrom DE 196 27 801 C1.

Now, by means of the invention not only the contact points arrangedalong a straight-line scanning channel but also the contact pointsdistributed over the surface area of the grid base are electricallyconnected.

Simulations have shown that in the case of large-area circuit boards,such as e.g. backplanes, the majority of the contact points 4 providedon the grid base are not electrical contacted, so that that any multipleassignment of the scanning channels 9 interconnected electrically may besimply avoided whilst at the same time making a high density of contactpoints 4 available which is of advantage in crowded locations of circuitboard test points on the board under test.

The tester in accordance with the invention may be configured e.g. fortesting backplanes sized 1000 mm×600 mm. Such backplanes have e.g.roughly 20,000 circuit board test points needing to be contacted by thetester. Usual testers comprise a grid spacing of one-tenth of an inch sothat conventional testers comprise a grid pattern involving 160,000contact points, each of which needs to be connected to the electronicsof the tester. This is why these testers comprise electronics fortesting 160,000 contact points requiring a correspondingly high numberof electronics cards. Now, due to linking the contact points 4 in thetest zone in accordance with the invention a plurality of contact pointsare connected jointly to but a sole input of tester electronics in eachcase, thus permitting a drastic reduction in the number of electronicscards required whilst still enabling all contact points 4 of the testerin contact with the circuit board being tested to be properly signalled.

With the configuration of a tester in accordance with the invention itis now o also possible to provide such large test zones with anincreased contact point density, e.g. double contact point density,without needing to increase the electronics accordingly. Such anincrease in contact density is expedient when contact point zones havingcrowded locations are provided on the circuit board, as is necessary,e.g. in the case of advanced highly integrated ICs.

Yet another advantage afforded by the invention is that the electricalconnections between the scanning channels 9 may now be varied by varyingthe arrangement of the contact pins 17 in the bus adapter 14 to thuspermit generating on a single grid base 2 differing linkages of thecontact points 4 in the test zone 1 1 tailored to the circuit boardbeing tested.

It will be appreciated that the invention is not restricted to theexample embodiment as detained above, instead also an embodiment inwhich the electronics cards are connected to the bus board is likewisewithin the scope of the present invention, for example, whereby busadapter and bus board are arranged below the grid base, for instance. Itis also possible that the bus board is provided with insertion pins fordirect insertion into the hollow test connections configured uncoveredin the connection zone 12. In such an embodiment no adapter is neededsince the bus board is directly connected to the grid base. However, anyother connecting technique is possible with the invention forselectively electrically connecting the scanning channels. For instance,the bus adapter may be configured as a rubber adapter, one such rubberadapter being a elastic rubber board having electrically conductingsections electrically connecting the scanning channels to the busconductors.

What is claimed is:
 1. A tester for testing a large-area,non-componented printed circuit board having a plurality of test points,comprising: an electronic analyzer comprising a plurality of testconnections; a grid base having a side provided with a grid patterncomprising a plurality of contact points arranged in a predeterminedpattem, each of said contact points being electrically connected to atleast one of a plurality of straight-line scanning channels, whereinseveral of said contact points are electrically connected to eachstraight-line scanning channel and wherein an electrical connection canbe made between said test points and at least some of said contactpoints when an adapter and/or a translator is mounted between said gridpattern and said printed circuit board being tested; and a means forelectrically connecting a plurality of scanning channels together toform groups of electrically connected scanning channels, wherein eachgroup of electrically connected scanning channels is connected to one ofsaid test connections of said electronic nalyzer.
 2. The tester as setforth in claim 1, wherein said means for electrically connecting aplurality of scanning channels together comprises a bus board comprisingseveral bus conductors running preferably in parallel to said scanningchannels which may be selectively brought into contact with saidscanning channels.
 3. The tester as set forth in claim 2, wherein a busadapter is arranged between said bus board and said grid pattern.
 4. Thetester as set forth in claim 2, wherein said bus board is provided withcontact elements for directly contacting said scanning channels.
 5. Thetester as set forth in claim 2, wherein said grid base comprises a testzone in which said contact points connected to said scanning channelsare arranged for electrically contacting the test points of a circuitboard to be tested and a connection zone in which further contact pointsconnected to said scanning channels are provided for contacting said busconductors.
 6. The tester as set forth in claim 4, wherein said gridbase comprises a test zone in which said contact points connected tosaid scanning channels are arranged for electrically contacting saidtest points of a circuit board to be tested and a connection zone inwhich further contact points connected to said scanning channels areprovided for contacting said bus conductors.
 7. The tester as set forthin claim 5, wherein contact points for contacting said electronicanalyzer are provided in said connection zone on a side of said gridbase opposite to said side of said grid base provided with contactpoints for contacting said bus conductors.
 8. The tester as set forth inclaim 6, wherein contact points for contacting said electronic analyzerare provided in said connection zone on a side of said grid baseopposite to said side of said grid base provided with contact points forcontacting said bus conductors.
 9. The tester as set forth in claim 7,wherein said contact points are arranged in opposing pairs on said gridbase and each contact point in an opposing pair is connected to ascanning channel separate from the other.
 10. The tester as set forth inclaim 8, wherein said contact points are arranged in opposing pairs onsaid grid base and each contact point in an opposing pair is connectedto a scanning channel separate from the other.
 11. The tester as setforth in claim 5, wherein said test zone has a surface area of at least250,000 mm².
 12. The tester as set forth in claim 10, wherein said testzone has a surface area of at least 250,000 mm².
 13. A printed circuitboard tester comprising: a grid base having a grid pattern providedthereon, said grid pattern comprising contact points arranged in apredetermined pattern, several of said contact points being electricallyconnected to each of a plurality of straight-line scanning channels; anelectronic analyzer having a plurality of test connections; and a meansfor electrically connecting a plurality of said scanning channelstogether to form groups of electrically connected scanning channels,each group of electrically connected scanning channels being connectedto only one of said test connections of said electronic analyzer.